A continuing goal in semiconductor processing is to reduce the amount of semiconductor wafer real estate consumed by integrated circuit devices. Exemplary integrated circuit devices are memory devices, such as, for example, DRAM devices. The DRAM devices are typically provided in arrays, with individual memory units comprising a transistor and a capacitor. Each individual DRAM unit of the array is provided with a unique address, which enables the individual units to be separately accessible relative to one another for reading and writing memory bits. It would be desirable to develop novel constructions of DRAM devices which reduce an amount of semiconductor real estate associated with the devices.